• Statistics, Analytics and Machine learning • Project management, business development, mentoring, decisions making. • Static Timing analysis and sign off for Multi million gates at lower nodes and low power • Multi Mode Multi Corner (MMMC ) analysis • Synthesis and STA • ASIC design • Knowledge on ASIC design flow ( Synthesis to GDSII) • Scripting in TCL, AIM • Analytics and data mining Other analysis for STA sign off ------------------------ o Advanced sign off analysis: AOCV and POCV o IR drop analysis o Parasitic extraction o Usage of different ECOs o PrimeTime PX for power analysis- to achieve low power solution o Low power implementation Low Power and Knowledge on CMOS • Analog design and analysis o Bandgap Reference circuit o LDO design o DC DC converter o Behavioral AMS modeling using VHDL-AMS and MAST o Statistical analysis like sensitivity, Monte Carlo • M.Tech from IIT Bombay ================= Conference and patents ================= • 6 conference papers (International and national including IEEE) • total 6 patents including (Accurate load prediction of processor for Dynamic Voltage and Frequency Scaling (DVFS)-2014-15 India ( 1702/MUM/2015), USA and UK )
Product Manager, Tata Consultancy Services
Aug 2012 to Present
1.Analytics and data mining 2.Product management,Manages different sprints ========================== Syntheiss and Static Timing Analysis (Sign off for multi million gates at lower node, AOCV, Multi Mode Multi Corner analysis(MMMC) , cross talk analysis • Complete Knowledge on ASIC design flow ( Synthesis to GDSII) Advanced Analysis o AOCV, POCV, PBA o parasitic extraction (STAR RC) Low Power implementation Strong knowledge on front end ASIC design and complete knowledge on ASIC design flow. • Analog design and analysis o Behavioral AMS modeling using VHDL-AMS and MAST o Statistical analysis like sensitivity, Monte Carlo Patents Published ============== (Patent Filed) Accurate load prediction of processor for Dynamic Voltage and Frequency Scaling(DVFS)- Dec 2014, India( 1702/MUM/2015), (Patent Filed) Work load Optimization of processor for low power (USA) (Patent Filed) Work load Optimization of processor for low power (Europe) (Patent Accepted) System and method to analyze OSS compliance software product deliverable Oct -2015 (Patent submitted) Sensitivity and Monte Carlo Analysis Guides for Mass Production in Industry Dec-2015 (Patent under review) Model fitting to Time series cluster. Conference /Journal publications: ================= (Submitted) Sensitivity and Monte Carlo Analysis Guides for Mass Production in Industry June-2016 ( IEEE conf) Designing 42/14V Buck Converter for Automotive Bus Architecture, at International Conference on Power Electronics Technology in Nov 2007 in Dallas, Texas. Maximum Power Tracking of Solar cells used for car, at International Conference on Power Electronics Technology in Oct 2006 at Long Beach, California. 42V Technology, the solution for the future car International CAE Conference of General Motor. July 2005 Calculation of Break Even Power (BEP) for solar cells between fixed axis and two axis tracking. July 2010, IIT Bombay.