Prashant Panda

Engineering manager at Tata Consultancy Services

Bhubaneswar, Odisha, India

Summary
Product Analytics Logic Synthesis Timing Closure Static Timing Analysis Data Science

• Statistics, Analytics and Machine learning
• Project management, business development, mentoring, decisions making.
• Static Timing analysis and sign off for Multi million gates at lower nodes and low power
• Multi Mode Multi Corner (MMMC ) analysis
• Synthesis and STA
• ASIC design
• Knowledge on ASIC design flow ( Synthesis to GDSII)
• Scripting in TCL, AIM
• Analytics and data mining
Other analysis for STA sign off
------------------------
o Advanced sign off analysis: AOCV and POCV
o IR drop analysis
o Parasitic extraction
o Usage of different ECOs
o PrimeTime PX for power analysis- to achieve low power solution
o Low power implementation
Low Power and Knowledge on CMOS

• Analog design and analysis
o Bandgap Reference circuit
o LDO design
o DC DC converter
o Behavioral AMS modeling using VHDL-AMS and MAST
o Statistical analysis like sensitivity, Monte Carlo

• M.Tech from IIT Bombay

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Conference and patents
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• 6 conference papers (International and national including IEEE)
• total 6 patents in analytics and VLSI including (Accurate load prediction of processor for Dynamic Voltage and Frequency Scaling (DVFS)-2014-15 India ( 1702/MUM/2015), USA and UK )

Experience

Engineering Manager at Tata Consultancy Services

Aug 2012 - Present

1. Analytics and data mining, statistics 2. Implementation of analytics from concept to final level in different products. 3. Time series forecasting, predictive analytics 4. Coaching different employee in Analytics 5. Product management,Manages different sprints ========================== Patents Published ============== 1. (Patent Filed) Accurate load prediction of processor for Dynamic Voltage and Frequency Scaling(DVFS)- Dec 2014, India( 1702/MUM/2015), 2.(Patent Filed) Work load Optimization of processor for low power (USA) 3. (Patent Granted) Work load Optimization of processor for low power (Europe) 4. (Patent Accepted) System and method to analyze OSS compliance software product deliverable Oct -2015 5. (Patent Filed) Model fitting to Time series cluster. 6. (Patent submitted) Sensitivity and Monte Carlo Analysis Guides for Mass Production in Industry Dec-2015 ====================== Conference /Journal publications: ===================== 1. Sensitivity and Monte Carlo Analysis Guides for Mass Production in Industry June-2016 ( IEEE conf) 2. Designing 42/14V Buck Converter for Automotive Bus Architecture, at International Conference on Power Electronics Technology in Nov 2007 in Dallas, Texas. 3. Maximum Power Tracking of Solar cells used for car, at International Conference on Power Electronics Technology in Oct 2006 at Long Beach, California. 42V Technology, the solution for the future car 4. International CAE Conference of General Motor. July 2005 5. Calculation of Break Even Power (BEP) for solar cells between fixed axis and two axis tracking. July 2010, IIT Bombay. =========================== Education ============ 1. M.Tech from IIT Bombay in 2003 2. B.Tech from CET Bhubaneswar =========================== 1. Syntheiss and Static Timing Analysis (Sign off for multi million gates at lower node, AOCV, Multi Mode Multi Corner analysis(MMMC) , cross talk analysis • Complete Knowledge on ASIC design flow ( Synthesis to GDSII) Advanced Analysis o AOCV, POCV, PBA o parasitic extraction (STAR RC) 2. Low Power implementation Strong knowledge on front end ASIC design and complete knowledge on ASIC design flow. 3. Analog design and analysis o Behavioral AMS modeling using VHDL-AMS and MAST o Statistical analysis like sensitivity, Monte Carlo

Education

Power Electronics at IIT Bombay

Jun 2001 - Jun 2003

Electrical Engineering at College of Engg & Technology

Jun 1996 - Jun 2000

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