Nikhil Puri

R&D Engineer II (Silicon compiler Memory Design) @ Synopsys

Noida Area, India

Summary
Synopsys Custom Compiler Logic and memory chip plants support VLSI CAD Digital CMOS VLSI Design Semiconductors
I'm a very enthusiastic learner. Take every challenge head on.
> Characterization of Silicon compiler for SRAM memory
> Process entitlement.
> Bitcell Analysis, SNM, Write Margins, EWT Methodology, Read Current analysis usign Hspice.
> Timing and Power Analysis/Verification of FullRC extracted Memory Instances using Hsim/XA
> Read/Write Assist Circuits to help read and write at worst case corners and analysis on improving the write assist circuitry.
> Worked on 16nm/14nm FinFet technology, analysis of RC with technology. Also worked on 10nm dual mask technology.
> Worked on various margins in the memory circuits and Analysis of different blocks like level shifter, level detector, sense amp and power-down/leakage saving modes.
> Writing spice measurements for memory compilers.
Experience

R & D Engineer II at Synopsys Inc

May 2015 - Present

Education

M.tech at Thapar University

Jun 2010 - Jun 2012

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