Ramdas Mozhikunnath

Experienced Verification Engineer, Intel Alumni, Online Teacher, Author

Bengaluru, Karnataka, India

Summary
Technology Careers Digital hardware design Verification Engineer UVM ASIC SystemVerilog Computer Architecture Interview Preparation
1) Experienced Verification engineer with 17+ years of experience in pre-silicon and post-silicon verification of complex ASIC and microprocessors with a passion for continuous learning and building technical knowledge.

2) Expertise in microprocessor cores, caches, coherency and memory sub-system micro architecture and verification along with deep understanding of Verification methodologies and programming languages like SystemVerilog, C++, OVM , UVM etc.

3) Co-Author of the Book - "Cracking Digital VLSI Verification Interview: Interview Success" - A golden reference guide for Verification Engineers at all experience level (Available both kindle/paperback - For details refer - http://verificationexcellence.in/books )

4) Passionate in Training and knowledge sharing on Functional Verification - both online and offline. Follow my website - www.verificationexcellence.in for online courses on Verification, SystemVerilog, Assertions and UVM.

5) Active Quora blogger on VLSI and related topics - Selected as Quora Top Writer 2017
https://www.quora.com/profile/Ramdas-Mozhikunnath
Experience

PMTS Design Verification Engineer at AMD

Dec 2017 - Present

Design Verification of next generation Systems IP for AMD server/client products

Senior Verification Engineer / Manager at Applied Micro Circuits Corporation

Dec 2013 - Nov 2017

Everything needed for successful silicon for X-gene family of ARM server class SOC designs

Senior Staff Verification Engineer at Intel India Private Limited

Jun 2011 - Dec 2013

Verification of GPU for Intel Broadwell and Skylake family of microprocessors

Advisory Verification Engineer at IBM

Dec 2009 - May 2011

POWER 8 microprocessor Core Verification - Unit level verification for execution units, scheduler, core level verification, behavioral modelling

Staff Verification Engineer at Qlogic

Jun 2008 - Dec 2009

Joined QLogic as part of acquisition of Netxen by QLogic. Worked on verification of 10G intelligent NICs which supports TCP offload, Iscsi, Fcoe offloading.

Design Verification Engineer at Montalvo Systems

Jan 2006 - May 2008

Verification of x86 microprocessor core Ioad/store execution units, caches(DL1,DL2), TLBs etc for multicore microprocessor chip - Everything from test plans to test bench development, execution, debug and closure

Design Verification Engineer at Intel India Private Limited

Jul 2001 - Dec 2005

Design verification of multi core microprocessor - Involved in verification of Cache coherency, FB-DIMM memory controller, Physical layer and DFT/DFM Design verification and emulation of Ethernet switches - Involved in emulation setup and bring up for Gigabit ethernet switch and verification of MAC and other data paths. Silicon debug for ethernet switches - Involved in post-silicon bring up, debug and performance validation of ethernet switches

Research Engineer at CDOT (Center for Development of Telematics)

Jul 1999 - Jun 2001

System level Board , FPGA design, debug. - Involved in system level design and debug for ATM telecom switches, FPGA design for MPC8260 based system designs, device selection and schematic capture for board design

Education

B Tech Electronics & Communication Engineering at NIT Calicut

May 1995 - May 1999

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