Good work experience in front-end (RTL, DC, DFT, etc.) domain of chip design with strong expertise in DFT domain. Strong knowledge of back-end flows with expertise in STA. In my latest role, I work as Design Manager for testchips and multi-foundry designs working closely with cross-domain leads, team members and global team in US. In-depth knowledge and hands on working experience on all DFT aspects: - SoC DFT design / architecture - ATPG - CDN ET, Mentor TK, Synopsys TMAX - JTAG - Memory BIST - AMS : Analog Mixes Signal - DFT RTL design : Designed on chip clock generate for a multi-million gate SoC at TI. - ATE - Silicon bring up : Wafer Test, Package Test - RTP of a device : Support RMA, bring up, multi fab bring up, increase yield. Worked on following technology nodes : 90nm, 65nm, 45nm, 28nm 20nm and lower tech nodes. Other: - Very efficient at leading and working with CWF team in both ODC and on-site model. - Successfully worked with teams across the globe: France, Dallas, Taiwan, San-diego, Austin, etc. - People management skills, leading a team of senior experienced professionals
Design Manager, Qualcomm
Jan 2013 to Present
Working as Design Manager for Testchip across latest cutting edge technology nodes across multiple foundry houses. Own the development and deployment of Multi-foundry designs.
DFT Manager, Texas Instruments
Oct 2006 to Jan 2013
Worked on DFT architecture and methodologies for OMAP chipsets. Specialized in OMAP3 and OMAP4 test architecture. Owned the RAMP of these devices from silicon to Customer Production. Built the DFT organization and working SoWs, SLAs with our contract work force team across multiple vendors.
MBA - Marketing, Manipal, Bangalore
May 2009 to May 2011
B.E. Electronics and Communication, Netaji Subhas Institute of Technology, NSIT Delhi
May 2001 to May 2005