Hardware Designer at IBM India Private Limited
Jan 2015 - Present
Develop and Support I/O Models for Full System Simulation needed by the Power Hypervisor Virtual Platform for the Power Server Family of product.
Hardware Design Engineer at CISCO India Pvt Ltd.
Aug 2013 - Nov 2014
ASIC Design Verification Team. 1. Currently working on block level verification for complex ASIC meant for core/edge routers. 2. Involved in end to end verification including testplan developement, fully random SV/UVM based Testbench design & coverage closure.
M. E. Embedded Systems at BITS, Pilani
Jul 2011 - Jun 2013
B.Tech ECE at Bharati Vidyapeeth's College of Engineering, New Delhi
Jul 2007 - May 2011