Aloysius Abreo

Physical Design Engineer at Intel India Technology Pvt Ltd

Bengaluru Area, India

Summary
Digital hardware design Cadence Schematic Capture PCB layout design Component Development Physical Design

Working full time as a Digital Design engineer, SoC Physical backend design at Intel Technologies Pvt. Ltd. in Bangalore. Previously worked as a platform designer for reference validation platforms used to validate next generation SoCs. Interned in the same company before joining. Understanding includes Core Electronics concepts with increasing exposure to industry based technology standards and products.

Experience

Physical Design Engineer at Intel Technology Pvt. Ltd.

Nov 2017 - Present

Working on execution for next generation SoC physical design.

Design Engineer at Intel India Technology Pvt Ltd

May 2016 - Nov 2017

Platform designer for High speed IO interfaces

Education

B. E. (Hons.) Electronics and Electrical Engineering at BITS Pilani

Aug 2012 - Aug 2016

Bachelor's Degree

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