Abhijeet Chandratre

Sr. ASIC Design Engineer at NVIDIA

Bengaluru Area, India

Digital hardware design Verification Low Power Design Static Timing Analysis RTL Design Verilog Perl
- Low Power Architecture and Design for GPUs (discrete/integrated).
- Heatmap analysis for mobile processors (Tegra).
- High/Low Frequency Noise Analysis for discrete GPUs in RTL/Emulation stage at unit and fullchip level respectively.
- Static Low Power Verification and clamp/level-shifter insertion for Mobile Processors as per UPF standards.
- Dynamic Verification (mostly Low Power) at RTL/Gate-Level for GPU.
- Infrastructure development and automation across multiple platforms.
- Study of the variable data rate digital demodulator and design of the timing recovery of the same (for given specifications).

Sr. ASIC Design Engineer at NVIDIA

Aug 2014 - Present

Involved in architecture and design of low-power methodologies for the advanced process nodes for discrete and integrated GPUs. Developing methodology to generate temperature maps for partitions for general use-cases for mobile processors (Tegra).


Masters of Engineering, Microelectronics at BITS Pilani, Hyderabad

Jul 2009 - Apr 2011

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